ChangXin Memory Technologies says it plans to unveil a DDR5 registered memory module using a new 4F² DRAM cell structure by the end of 2026, intensifying competition in server memory. The Chinese chipmaker says it has developed a vertical surrounding-gate transistor to address leakage problems associated with the denser design, but has not disclosed detailed specifications or production results.
A 4F² cell occupies about one-third less area than the 6F² structure widely used in current DRAM. That could allow more data to fit on a chip of the same size. CXMT is targeting server RDIMMs rather than lower-power mobile memory, a choice that places the technology in a market requiring continuous operation and reliable high-speed data transmission.
Independent industry assessments cited in live coverage said the company’s process, yields, performance and ability to sustain mass production cannot yet be verified from the information disclosed.
The development comes as SanDisk is pursuing a different memory opportunity built on NAND flash. Its High Bandwidth Flash architecture is intended as a memory tier between high-bandwidth memory and conventional storage for AI inference, combining stacked NAND capacity with a high-speed interface.
SanDisk and SK hynix released an HBF technical specification through the Open Compute Project in August 2026. The specification covers interfaces, electrical requirements, packaging, reliability and software operations, and allows 8-high or 16-high NAND stacks with capacities of up to 512GB.
Analysis: CXMT’s announcement adds to competitive pressure in the broader memory market, but it does not by itself show that SanDisk’s NAND business or HBF plans have been impaired. The next concrete milestones are CXMT’s promised product unveiling and SanDisk’s planned HBF sampling schedule.