SpacemiT introduced its V100 server processor on Oct. 20 at RISC-V Summit China 2026, pairing the 46-core chip with three systems aimed at general-purpose computing, AI acceleration and storage. The launch marks the company’s expansion from device and edge processors into data-center hardware.
A cache-coherent interconnect allows two processors to operate in one server for configurations of up to 92 cores.
SpacemiT says the processor is the first general-purpose chip to fully comply with RISC-V server specifications, including the RVA23 profile, server SoC and platform requirements, Boot and Runtime Services, and the RISC-V Security Model. The company says the V100 passed all BRS compliance tests and can run mainstream Linux distributions, while hardware support covers CPU, interrupt and I/O virtualization, upstream Linux KVM, a hardware root of trust and server reliability features.
The accompanying C2201, G5201 and S5236 platforms are designed for computing, intelligent computing and large-scale storage. The G5201 can hold eight full-height, full-length, double-width accelerator cards, has been validated with Kunlunxin and other accelerators, and supports RDMA networking for high-speed clusters. SpacemiT is also offering motherboard reference designs, firmware, baseboard-management support and hardware documentation for system builders.
Software support is part of the launch. It is working with Canonical, the RISE Project and Scaleway to provide developers with access to RVA23-compatible hardware through shared K3 compute clusters.
The V100 follows earlier work on SpacemiT’s X100 server-grade core. That figure was reported for the core, not as a benchmark result for the complete 46-core V100. Independent coverage of the launch also noted that full V100 performance testing had not yet been reported.